A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells

This paper describes the design and development of a module generator for a dual-rail PLA with embedded 2-input logic cells for 0.35 μm CMOS technology. In order to automatically generate logic-cell based PLA layouts from circuit specifications, a module generator as a design automation tool of logic-cell based PLA is developed with a structural improvement. This module generator is based on a timing-driven design methodology and consists of logic synthesis, transistor sizing and logic cell generation, stimulus generation, HDL model generation parts. This generator uses a design constraint to achieve a flexible transistor sizing in a logic cell generation part. In addition, generated logic cells can be easily adapted to a layout generator. The layout is generated by using 0.35μm, 3-metal-layer CMOS technology. Moreover, an HDL model generator is developed to create delay behavior models easily and quickly with precise timing parameters. The design complexity which is becoming an important issue for VLSI circuits can be reduced partially and human caused errors are minimized by module generator. A PLA layout in GDS-II form and an HDL model behavior of a Boolean function which has 64-bit input, 1bit output and 220 product term can be generated within 8 minutes on a SunUltraSPARC-III 900MHz processor. A very short time is required to compile the module, and this makes it feasible for designers to try many different design configurations in order to get the better one. key words: PLA, module generator, cell generation, HDL behavior generation